1. Field of the Invention
The present invention relates to a circuit modification method of modifying a circuit when a glitch having an unacceptable level occurs in a wire within the circuit under the influence of other wires.
2. Description of the Prior Art
In the case where a wire 2 is located in the vicinity of another wire 1 within a semiconductor integrated circuit, as shown in FIG. 1(a), if a voltage change occurs in the wire 2, a pulsed signal wave can occur in the wire 1 because of a coupling capacity between these wires. This phenomenon is known as “glitch”. A wire influenced by another wire is called victim, and a wire that influences another wire is called aggressor. In the case of FIGS. 1(a) and 1(b), the wire 1 is a victim, and the other wire 2 is an aggressor.
FIG. 2 shows voltage changes in the wires 1 and 2 when a glitch occurs in the wire 1. The horizontal axis of this graph indicates time, and the vertical axis indicates voltage values. With the wire 1 fixed to a power-supply voltage (1.5 Volts) by a driver 3, for example, when another driver 4 causes the voltage of the wire 2 to change from the power-supply voltage (1.5 Volts) to a ground voltage (0 Volts), there causes a glitch in the wire 1, the voltage of which drops once and then returns to the power-supply voltage, because of the coupling capacity Cc between the two wires 1 and 2. When a maximum amount of voltage change caused in the wire 1 is assumed to be the amount of glitch, there is a possibility that the next stage of the circuit connected to the wire 1 malfunctions because of the glitch if the amount of glitch is too large. Therefore, it is necessary to determine that a glitch error occurs when the amount of glitch exceeds a certain acceptable level, and to modify the circuit so as to reduce the amount of glitch. In the case where the wire 1 is fixed to a ground voltage, when the wire 2 changes from the ground voltage to the power-supply voltage, a glitch can similarly occur in the wire 1.
A glitch analysis method is disclosed by Rafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul and Vladimir Zolotov, “14.1 Clarinet: A noise analysis tool for deep submicron design”, p.233, (http://www.sigda.acm.org/Archives/ProceedingArchives/Dac/D ac2000/papers/2000/dac00/htmfiles/sun_sgi/dacabs.htm#14—1).
There is, as a prior art circuit modification method, a technique of inserting only one buffer (i.e., driver) 5 at the midpoint of the wire 1, as shown in FIG. 1(b) so as to prevent a glitch error from occurring in the wire 1. Since the buffer insertion divides the coupling capacity Cc between the two wires 1 and 2 into the coupling capacity Cc1 between a wire 1a and the wire 2 and the coupling capacity Cc2 between a wire 1b and the wire 2, the wire 1 being divided into the wires 1a and 1b, the amounts of glitches to be caused in the wires 1a and 1b respectively can be lower than the amount of glitch to be caused in the wire 1 in the case of FIG. 1(a). The method of modifying the circuit can be implemented via a computer program.
However, when the other wire 2 is located in the vicinity of the wire 1 such that the other wire 2 is apart from the midpoint of the wire 1, e.g., when the other wire 2 is adjacent to the next-stage side of the wire 1 as shown in FIG. 3, if the buffer 5 is located at the midpoint A of the wire 1, the coupling capacity between the wire 1a, which is the one of the two parts of division far from the other wire 2, and the other wire 2 becomes too small, and the amount of glitch to be caused in the wire 1a becomes zero roughly. In contrast, the coupling capacity Cc2 between the wire 1b, which is the one nearer to the other wire 2, and the other wire 2 is almost equal to the coupling capacity Cc between the wires 1 and 2 in the case of FIG. 1(a), the amount of glitch to be caused in the wire 1b is hardly reduced. Other factors might increase the amount of glitch. It is therefore necessary to further insert another buffer at the midpoint of the wire 1b. 
In such a prior art circuit modification method, even if two adjacent wires have any relationship between them, since a step of inserting an additional buffer at the midpoint of a wire which is a victim is repeated until no glitch error occurs, the number of buffers to be inserted into the victim is increased. This results in an increase in either the area or power consumption of the circuit.
Since only one type of predetermined buffers are inserted into the victim in any case, either the area or power consumption of the circuit is increased if those inserted buffers have a larger driving ability than required. On the other hand, when the buffers do not have a sufficient driving ability, the glitch error cannot be eliminated and additional buffers are needed.